8051 Microcontroller Interrupt

Interrupt

• There are five interrupt sources for the 8051, which means that they can recognize 5 different events that can interrupt regular program execution. 
• there are five interrupts :,TF0,(INTR1)',TF1,RI/TI
• Each interrupt can be enabled or disabled by setting bits of the IE register. Likewise, the whole interrupt system can be disabled by clearing the EA bit of the same register. .
• Now, it is necessary to explain a few details referring to external interrupts- INT0 and INT1. If the IT0 and IT1 bits of the TCON register are set, an interrupt will be generated on high to low transition. 

Here we are mention vector address of interrupt.

 

IE Register (Interrupt Enable)

 

Priority level structure: 

Each interrupt source can be programmed to have one of the two priority levels by setting (high priority) or clearing (low priority) a bit in the IP (Interrupt Priority) Register.
A low priority interrupt can itself be interrupted by a high priority interrupt, but not by another low priority interrupt.
If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served.
If the requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced. Thus, within each priority level, there is a second priority level determined by the polling sequence, as follows.

 

IP Register (Interrupt Priority)

The IP register bits specify the priority level of each interrupt (high or low priority).

Interrupt handling:

• The interrupt flags are sampled at P2 of S5 of every instruction cycle (Note that every instruction cycle has six states each consisting of P1 and P2 pulses).
• The samples are polled during the next machine cycle (or instruction cycle). If one of the flags was set at S5P2 of the preceding instruction cycle, the polling detects it and the interrupt process generates a long call (LCALL) to the appropriate vector location of the interrupt. 
• The LCALL is generated provided this hardware generated LCALL is not blocked by any one of the following conditions. 

1. An interrupt of equal or higher priority level is already in progress.
2. The current polling cycle is not the final cycle in the execution of the instruction in progress.
3. The instruction in progress is RETI or any write to IE or IP registers.