8051 Microcontroller Interrupt

Interrupt

• There are five interrupt sources for the 8051, which means that they can recognize 5 different events that can interrupt regular program execution. 
• there are five interrupts :,TF0,(INTR1)',TF1,RI/TI
• Each interrupt can be enabled or disabled by setting bits of the IE register. Likewise, the whole interrupt system can be disabled by clearing the EA bit of the same register. .
• Now, it is necessary to explain a few details referring to external interrupts- INT0 and INT1. If the IT0 and IT1 bits of the TCON register are set, an interrupt will be generated on high to low transition. 

Here we are mention vector address of interrupt.

 

IE Register (Interrupt Enable)

 

Priority level structure: 

Each interrupt source can be programmed to have one of the two priority levels by setting (high priority) or clearing (low priority) a bit in the IP (Interrupt Priority) Register.
A low priority interrupt can itself be interrupted by a high priority interrupt, but not by another low priority interrupt.
If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served.
If the requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced. Thus, within each priority level, there is a second priority level determined by the polling sequence, as follows.

 

IP Register (Interrupt Priority)

The IP register bits specify the priority level of each interrupt (high or low priority).

Interrupt handling:

• The interrupt flags are sampled at P2 of S5 of every instruction cycle (Note that every instruction cycle has six states each consisting of P1 and P2 pulses).
• The samples are polled during the next machine cycle (or instruction cycle). If one of the flags was set at S5P2 of the preceding instruction cycle, the polling detects it and the interrupt process generates a long call (LCALL) to the appropriate vector location of the interrupt. 
• The LCALL is generated provided this hardware generated LCALL is not blocked by any one of the following conditions. 

1. An interrupt of equal or higher priority level is already in progress.
2. The current polling cycle is not the final cycle in the execution of the instruction in progress.
3. The instruction in progress is RETI or any write to IE or IP registers.

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Timer & Counter control Logics of 8051 Microcontroller

TIMING 

• If a counter is programmed to be a timer, it will count the internal clock frequency of the 8051 oscillator divided by 12d. 
• As an example, if the crystal frequency is 6.0 megahertz, then the timer clock will have a frequency of 500 kilohertz.
• The resultant timer clock is gated to the timer by means of the circuit shown in Figure. 
• In order for oscillator clock pulses to reach the timer, the C/(T)' bit in the TMOD register must be set to 0 (timer operation). 
• Bit TRX in the TCON register must be set to 1 (timer run), and the gate bit in the TMOD register must be 0, or external pin (INTX)' must he a 1. 
• In other words, the counter is configured as a timer, then the timer pulses are gated to the counter by the run bit and the gate bit or the external input bits (INTX)'

 

COUNTING

• The only difference between counting and timing is the source of the clock pulses to the counters. When used as a timer, the clock pulses are sourced from the oscillator through the divide-by-12d circuit.
• When used as a counter, pin T0 (P3.4) supplies pulses to counter 0. and pin T1 (P3.5) to counter 1.
• The C/(T)' bit in TMOD must be set to 1 to enable pulses from the TX pin to reach the control circuit shown in above Figure .
• The input pulse on TX is sampled during P2 of state 5 every machine cycle. A change on the input from high to low between samples will increment the counter.
• Each high and low state of the input pulse must thus be held constant for at least one machine cycle to ensure reliable counting. Since this takes 24 pulses, the maximum input frequency that can be accurately counted is the oscillator frequency divided by 24. for our 6 megahertz crystal. the calculation yields a maximum external frequency of 250 kilohertz.

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Timer & Counter of 8051 Microcontroller

Counters and Timers

Many microcontroller applications require the counting of external events, such as the frequency of a pulse train, or the generation of precise internal time delays between com­puter actions. Both of these tasks can be accomplished using software techniques, but software loops for counting or timing keep the processor occupied so that other, perhaps more important, functions are not done. To relieve the processor of this burden, two 16-bit up counters, named T0 and T1, are provided for the general use of the programmer. Each counter may be programmed to count internal clock pulses, acting as a timer, or pro­grammed to count external pulses as a counter. 

 

TCON(TIMER/COUNTER CONTROL REGISTER)

1. To control the timer/counter we need TCON register.
2. its bit addressable
3. address:88h

 

TMOD(THE TIMER MODE CONTROL REGISTER)

1. it dedicated two timer.
2. it is byte addressable
3. address:89h

 

Timer Mode

The timers may operate in anyone of four modes that are determined by the mode bits, M I and MO, in the TMOD register. Figure 12 shows the four timer modes.

Timer Mode 0

• Setting timer X mode bits to 00b in the TMOD register.
• theTHX register as an 8-bit counter and TLX as a 5-bit counter.
• As an example, the 6 megahertz oscillator frequency would result in a final frequency to TH of 15625 hertz. 
• The timer flag is set whenever THX goes from FFh to 00h

Timer Mode 1

• the mode bits are set to 0lb in TMOD
• Mode 1 is similar to mode 0 except TLX is configured as a full 8-bit counter when .

Timer Mode 2

• Setting the mode bits to l0b in TMOD configures.
• the timer to use only the TLX counter as an 8-bit counter. 
• THX is used to hold a value that is loaded into TLX every time TLX overflows from FFh to 00h. The timer flag is also set when TLX overflows.
• This mode exhibits an auto-reload feature: TLX will count up from the number in THX. overflow. and be initialized again with the contents of THX.

Timer Mode 3

• Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0. Timer0 in mode-3 establishes TL0 and TH0 as two separate counters.
• Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and TF0 are available to Timer-0 lower 8 bits(TL0). 

figure of Timer Modes

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Related Topics:

-> Function of microcontroller 8051 ports
-> what is RS-232
-> How to install Android Apps

-> How to install Keil
-> Internal RAM structure of 8051 comtroller 

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Branch Instruction Of 8051 controller

Branch Instructions

There are two kinds of branch instructions:

Unconditional jump instructions: upon their execution a jump to a new location from where the program continues execution is executed.

Conditional jump instructions: a jump to a new program location is executed only if a specified condition is met. Otherwise, the program normally proceeds with the next instruction.

ACALL addr11 - Absolute subroutine call

addr11: Subroutine address

Description: Instruction unconditionally calls a subroutine located at the specified code address. Therefore, the current address and the address of called subroutine must be within the same 2K byte block of the program memory, starting from the first byte of the instruction following ACALL.

EXAMPLE:

Before execution: PC=0123h
After execution: PC=0345h

AJMP addr11 - Absoulte jump

addr11: Jump address

Description: Program continues execution after executing a jump to the specified address. Similar to the ACALL instruction, the jump must be executed within the same 2K byte block of program memory starting from the first byte of the instruction following AJMP.

EXAMPLE:

Before execution: PC=0345h SP=07h
After execution: PC=0123h SP=09h

CJNE A,direct,rel - Compares direct byte to the accumulator and jumps if not equal

A: accumulator
 Direct: arbitrary register with address 0-255 (0-FFh)
 addr: jump address

Description: Instruction first compares the number in the accumulator with the directly addressed byte. If they are equal, the program proceeds with execution. Otherwise, a jump to the specified address will be executed. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-128 to +127 locations relative to the first following instruction).

EXAMPLE:

Before execution: PC=0145h A=27h
After execution: if MAX≠27: PC=0123h
If MAX=27: PC=0146h

CJNE A,#data,rel - Compares immediate data to the accumulator and jumps if not equal

A: accumulator
 Data: constant in the range of 0-255 (0-FFh)

Description: Instruction first compares the number in the accumulator with the immediate data. If they are equal, the program proceeds with execution. Otherwise, a jump to the specified address will be executed. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-128 to +127 locations relative to the first following instruction).

EXAMPLE:

Before execution: PC=0445h
After execution: If A≠33: PC=0423h
If A=33: PC=0446h

CJNE Rn,#data,rel - Compares immediate data to the register Rn and jumps if not equal

Rn: Any R register (R0-R7)
 Data: Constant in the range of 0 - 255 (0-FFh)
 addr: Jump address

Description: Instruction first compares immediate data to the register Rn. If they are equal, the program proceeds with execution. Otherwise, a jump to the specified address will be executed. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-128 to + 127 locations relative to the first following instruction).

EXAMPLE:

Before execution: PC=0345h
After execution: If R5≠44h: PC=0323h
If R5=44h: PC=0346h

CJNE @Ri,#data,rel - Compares immediate data to indirectly addressed register and jumps if not equal

Ri: Register R0 or R1
 Data: Constant in the range of 0 - 255 (0-FFh)

Description: This instruction first compares immediate data to indirectly addressed register. If they are equal, the program proceeds with execution. Otherwise, a jump to the specified address in the program will be executed. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-128 to +127 locations relative to the next instruction).

EXAMPLE:

Before execution: Register Address SUM=F3h
PC=0345h R0=F3h
After execution: If SUM≠44h: PC=0323h
If SUM=44h: PC=0346h

DJNZ direct,rel - Decrements direct byte by 1 and jumps if not 0

Direct: arbitrary register with address 0-255 (0-FFh)
 addr: Jump address

Description: This instruction first decrements value in the register. If the result is 0, the program proceeds with execution. Otherwise, a jump to the specified address in the program will be executed. As it is direct addressing, the register must be within the first 255 locations of RAM. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-128 to +127 locations relative to the first following instruction).

EXAMPLE:

Before execution: PC=0445h
After execution: If CNT≠0: PC=0423h
If CNT=0: PC=0446h

DJNZ Rn,rel - Decrements the Rn register by 1 and jumps if not 0

Rn: any R register (R0-R7)
 addr: jump address

Description: This instruction first decrements the value in the Rn register. If the result is 0, the program proceeds with execution. Otherwise, a jump to the specified address in the program will be executed. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (- 128 to +127 locations relative to the first following instruction).

EXAMPLE:

Before execution: PC=0445h
After execution: If R1≠0: PC=0423h
If R1=0: PC=0446h

JB bit,rel - Jump if direct bit is set

addr: Jump address
 Bit: any bit of RAM

Description: If the bit is set, a jump to the specified address will be executed. Otherwise, if the value of bit is 0, the program proceeds with the next instruction. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-128 to + 127 locations relative to the first following instruction).

EXAMPLE:

Before execution: PC=0323h
After execution: If P0.5=0: PC=0324h
If P0.5=1: PC=0345h

JC rel - Jump if carry flag is set

addr: Jump address

Description: Instruction first checks if the carry flag is set. If set, a jump to the specified address is executed. Otherwise, the program proceeds with the next instruction. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-129 to + 127 locations relative to the first following instruction).

EXAMPLE:

Before instruction: PC=0323h
After instruction: If C=0: PC=0324h
If C=1: PC=0345h

JBC bit,rel - Jump if direct bit is set

Bit: any bit of RAM
 addr: Jump Address

Description: This instruction first checks if the bit is set. If set, a jump to the specified address is executed and the bit is cleared. Otherwise, the program proceeds with the first following instruction. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-129 to + 127 locations relative to the first following instruction).

EXAMPLE:

Before execution: PC=0323h
After execution: If TEST0.4=1: PC=0345h, TEST0.4=0
If TEST0.4=0: PC=0324h, TEST0,4=0

JNB bit,rel - Jump if direct bit is not set

addr: Jump address
 Bit: any bit of RAM

Description: If the bit is cleared, a jump to the specified address will be executed. Otherwise, if the bit value is 1, the program proceeds with the first following instruction. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-129 to + 127 locations relative to the first following instruction).

EXAMPLE:

Before execution: PC=0323h
After execution: If P0.5=1: PC=0324h
If P0.5=0: PC=0345h

JMP @A+DPTR - Jump indirect relative to the DPTR

A: accumulator
 DPTR: Data Pointer

Description: This instruction causes a jump to the address calculated by adding value stored in the accumulator to the 16-bit number in the DPTR Register. It is used with complex program branching where the accumulator affects jump address, for example when reading a table. Neither accumulator nor DPTR register are affected.

EXAMPLE:

Before execution: PC=223 DPTR=1400h
After execution: PC = 1402h if A=2
PC = 1404h if A=4
PC = 1406h if A=6

Note:
As instructions AJMP LABELS occupy two locations each, the values in the accumulator specifying them must be different from each other by 2.

JNZ rel - Jump if accumulator is not zero

addr: Jump Address

Description: This instruction checks if the value stored in the accumulator is 0. If not, a jump to the specified address will be executed. Otherwise, the program proceeds with the first following instruction. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-129 to + 127 locations relative to the first following instruction).

EXAMPLE:

Before execution: PC=0323h
After execution: If A=0: PC=324h
If A≠0: PC=283h

JNC rel - Jump if carry flag is not set

addr: Jump Address

Description: This instruction first checks whether the carry flag is set. If not, a jump to the specified address will be executed. Otherwise, the program proceeds with the first following instruction. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-129 to + 127 locations relative to the first following instruction).

EXAMPLE:

Before execution: PC=0323h
After execution: If C=0: PC=360h
If C=1: PC=324h

LCALL addr16 - Long subroutine call

addr16: Subroutine Address

Description: This instruction unconditionally calls a subroutine located at the specified address. The current address and the start of the subroutine called can be located anywhere within the memory space of 64K.

EXAMPLE:

Before execution: PC=0123h
After execution: PC=1234h

JZ rel - Jump if accumulator is zero

addr: Jump Address

Description: The instruction checks whether the value stored in the accumulator is 0. If yes, a jump to the specified address will be executed. Otherwise, the program proceeds with the following instruction. This is a short jump instruction, which means that the address of a new location must be relatively near the current one (-129 to + 127 locations relative to the first following instruction).

EXAMPLE:

Before execution: PC=0323h
After execution: If A0: PC=324h
If A=0: PC=283h

LJMP addr16 - Long jump

addr16: jump address

Description: Instruction causes a jump to the specified 16-bit address.

EXAMPLE:

Before execution: PC=0123h
After execution: PC=1234h

RET - Return from subroutine

Description: This instruction ends every subroutine. After execution, the program proceeds with the instruction following an ACALL or LCALL.

EXAMPLE:

RETI - Return from interrupt

Description: This instruction ends every interrupt routine and informs processor about it. After executing the instruction, the program proceeds from where it left off. The PSW is not automatically returned its pre-interrupt status.

SJMP rel - Short Jump (relative address)

addr: Jump Address

Description: Instruction enables jump to the new address which should be in the range of -128 to +127 locations relative to the first following instruction.

EXAMPLE:

Before execution: PC=323
After execution: PC=345

Next Post:       Data Transfer Instruction
Previous Post:Arithmetic Instruction
 
Related Topics:

-> Function of microcontroller 8051 ports
-> what is RS-232
-> How to install Android Apps

-> Program Status Word-(PSW) of 8051
-> Internal RAM structure of 8051 comtroller 

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Data Transfer Instruction of 8051 controller

Data Transfer Instruction of 8051

This instructions are used to copy the content of source operand to Destination operand

MOV A,Rn - Moves the Rn register to the accumulator

The instruction moves the Rn register to the accumulator. The Rn register is not affected.

EXAMPLE:

 

Before execution: R3=58h
After execution: R3=58h A=58h

MOV A,@Ri - Moves the indirect RAM to the accumulator

Description: Instruction moves the indirectly addressed register of RAM to the accumulator. The register address is stored in the Ri register (R0 or R1). The result is stored in the accumulator. The register is not affected.

EXAMPLE:

Register Address SUM=F2h R0=F2h
Before execution: SUM=58h
After execution: A=58h SUM=58h

MOV A,direct - Moves the direct byte to the accumulator

Description: Instruction moves the direct byte to the accumulator. As it is direct addressing, the register can be any SFRs or general-purpose register with address 0-7Fh. (0-127 dec.). After executing the instruction, the register is not affected.

EXAMPLE:

Before execution: Rx=68h
After execution: Rx=68h A=68h

MOV Rn,A - Moves the accumulator to the Rn register

Desription: Instruction moves the accumulator to the Rn register. The accumulator is not affected.

EXAMPLE:

Before execution: A=58h
After execution: R3=58h A=58h

MOV A,#data - Moves the immediate data to the accumulator

Desription: Instruction moves the immediate data to the accumulator.

EXAMPLE:

After execution: A=28h

MOV Rn,#data - Moves the immediate data to the Rn register

Description: Instruction moves the immediate data to the Rn register.

After execution: R5=32h

MOV Rn,direct - Moves the direct byte to the Rn register

Description: Instruction moves the direct byte to the Rn register. As it is direct addressing, the register can be any SFRs or general-purpose register with address 0-7Fh. (0-127 dec.). After executing the instruction, the register is not affected.

EXAMPLE:

Before execution: SUM=58h
After execution: SUM=58h R3=58h

MOV direct,Rn - Moves the Rn register to the direct byte

Description: Instruction moves the Rn register to the direct byte. As it is direct addressing, the register can be any SFRs or general-purpose register with address 0-7Fh. (0-127 dec.). After executing the instruction, the register is not affected.

EXAMPLE:

Before execution: R3=18h
After execution: R3=18h CIF=18h

MOV direct,A - Moves the accumulator to the direct byte

Description: Instruction moves the accumulator to the direct byte. As it is direct addressing, the register can be any SFRs or general-purpose register with address 0-7Fh. (0-127 dec.). After executing the instruction, the register is not affected.

EXAMPLE:

Before execution: A=98h
After execution: A=98h REG=98h

MOV direct,@Ri - Moves the indirect RAM to the direct byte

Description: Instruction moves the indirectly adressed register of RAM to the direct byte. The register is not affected.

EXAMPLE:

Register Address SUM=F3
Before execution: SUM=58h R1=F3
After execution: SUM=58h TEMP=58h

MOV direct1,direct2 - Moves the direct byte to the direct byte

Description: Instruction moves the direct byte to another direct byte. As it is direct addressing, both registers can be any SFRs or general-purpose registers with address 0-7Fh. (0-127 dec.). The direct1 is not affected.

EXAMPLE:

Before execution: TEMP=58h
After execution: TEMP=58h SUM=58h

MOV @Ri,A - Moves the accumulator to the indirect RAM

Description: Instruction moves the accumulator to the indirectly addressed register of RAM. The register address is stored in the Ri register (R0 or R1). After executing the instruction, the accumulator is not affected.

EXAMPLE:

Register Address SUM=F2h
Before execution: R0=F2h A=58h
After execution: SUM=58h A=58h

MOV direct,#data - Moves the immediate data to the direct byte

Description: Instruction moves the immediate data to the direct byte. As it is direct addressing, the direct byte can be any SFRs or general-purpose register with address 0-7Fh. (0-127 dec.).

EXAMPLE:

After execution: TEMP=22h

MOV @Ri,#data - Moves the immediate data to the indirect RAM

Description: Instruction moves the immediate data to the idirectly addressed register of RAM. The register address is stored in the Ri register (R0 or R1).

EXAMPLE:

Register address TEMP=E2h
Before execution: R1=E2h
After execution: TEMP=44h

MOV @Ri,direct - Moves the direct byte to the indirect RAM

Description: Instruction moves the direct byte to a register the address of which is stored in the Ri register (R0 or R1). After executing the instruction, the direct byte is not affected.

EXAMPLE:

Register address TEMP=E2h
Before execution: SUM=58h R1=E2h
After execution: SUM=58h TEMP=58h

MOVC A,@A+DPTR - Moves the code byte relative to the DPTR to the accumulator

Description: Instruction first adds the 16-bit DPTR register to the accumulator. The result of addition is then used as a memory address from which the 8-bit data is moved to the accumulator.

EXAMPLE:

Before execution:
DPTR=1000:
A=0
A=1
A=2
A=3

After execution:
A=66h
A=77h
A=88h
A=99h

Note: DB (Define Byte) is a directive in assembly language used to define constant.

MOV DPTR,#data16 - Loads the data pointer with a 16-bit constant

Description: Instruction stores a 16-bit constant to the DPTR register. The 8 high bits of the constant are stored in the DPH register, while the 8 low bits are stored in the DPL register.

EXAMPLE:

After execution: DPH=12h DPL=34h

MOVX A,@Ri - Moves the external RAM (8-bit address) to the accumulator

Description: Instruction reads the content of a register in external RAM and moves it to the accumulator. The register address is stored in the Ri register (R0 or R1).

EXAMPLE:

Register Address: SUM=12h
Before execution: SUM=58h R0=12h
After execution: A=58h

Note:
SUM Register is stored in external RAM which is 256 bytes in size.

MOVC A,@A+PC - Moves the code byte relative to the PC to the accumulator

Description: Instruction first adds the 16-bit PC register to the accumulator (the current program address is stored in the PC register). The result of addition is then used as a memory address from which the 8-bit data is moved to the accumulator.

EXAMPLE:

After the subroutine "Table" has been executed, one of four values is stored in the accumulator:

Before execution:
A=0
A=1
A=2
A=3

After execution:
A=66h
A=77h
A=88h
A=99h

Note: DB (Define Byte) is a directive in assembly language used to define constant.

MOVX @Ri,A - Moves the accumulator to the external RAM (8-bit address)

Description: Instruction moves the accumulator to a register stored in external RAM. Its address is stored in the Ri register.

EXAMPLE:

 

Register address: SUM=34h

Before execution: A=58 R1=34h
After execution: SUM=58h

NOTE:
Register SUM is located in external RAM which is 256 bytes in size.

MOVX A,@DPTR - Moves the external memory (16-bit address) to the accumulator

Description: Instruction moves the content of a register in external memory to the accumulator. The 16-bit address of the register is stored in the DPTR register (DPH and DPL).

EXAMPLE:

Register address: SUM=1234h
Before execution: DPTR=1234h SUM=58
After execution: A=58h

Note:
Register SUM is located in external RAM which is up to 64K in size.

MOVX @DPTR,A - Moves the accumulator to the external RAM (16-bit address)

Description: Instruction moves the accumulator to a register stored in external RAM. The 16-bit address of the register is stored in the DPTR register (DPH and DPL).

EXAMPLE:

Register address: SUM=1234h
Before execution: A=58 DPTR=1234h
After execution: SUM=58h

Note:
Register SUM is located in RAM which is up to 64K in size.


Next Post:       Logical Instruction
Previous Post:Arithmetic Instruction

Related Topics:

-> Function of microcontroller 8051 ports
-> I/O PROGRAMMING OF 8051
-> Reset & Oscillator Circuit of 8051 Micro-Controller
-> Program Status Word-(PSW) of 8051
-> Internal RAM structure of 8051 comtroller

Read More